Reduced Instruction Set Computer - traduzione in spagnolo
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Reduced Instruction Set Computer - traduzione in spagnolo

PROCESSOR EXECUTING ONE INSTRUCTION IN MINIMAL CLOCK CYCLES
Reduced Instruction Set Computer; RISC processor; Reduced Instruction Set Code; Reduced Instruction Set Computing; RISC; RISC-based; RISC-based system; RISC System/6000 SP; Reduced instruction set; RISC architectures; RISC instruction set; RISC-based computer design approach; RISC principles; Reduced instruction set computing
  • An IBM [[PowerPC 601]] RISC microprocessor
  • The [[Sun Microsystems]] UltraSPARC processor is a type of RISC microprocessor.
  • RISC-V prototype chip (2013).

Reduced Instruction Set Computer         
RISC, Computador dueño de colección de ordenes reducidas, Procesador que el número de ordenes que es capaz de ejecutar se redució para permitir una frecuencia de trabajo más alta
instruction set         
  • One instruction may have several fields, which identify the logical operation, and may also include source and destination addresses and constant values. This is the MIPS "Add Immediate" instruction, which allows selection of source and destination registers and inclusion of a small constant.
SET OF ABSTRACT SYMBOLS (CALLED INSTRUCTIONS) WHICH IDENTIFY AND DESCRIBE OPERATIONS IN A COMPUTER PROGRAM TO A COMPUTER PROCESSOR
Instruction set architectures; Instruction Set Architecture; Instruction Set; Instruction (computer science); Register pressure; Load/store instruction; Load/Store instruction; Electronic action; Zero address machine; Zero-address machine; 0-operand instruction set; Instruction width; Code density; Instruction Sets; Instruction(s) (computer science); Instruction (computing); Native instruction; Variable-length instruction word; Variable-width instruction; Variable width instruction set; Variable width instruction; Variable-width instruction set; Variable length instruction set; Variable length instruction; Variable-length instruction set; Variable-length instruction; Fixed length instruction set; Fixed length instruction; Fixed-length instruction set; Fixed-length instruction; Fixed-width instruction; Fixed-width instruction set; Fixed width instruction; Fixed width instruction set; SIMD instruction; Arithmetic and logic operation; Arithmetic/logic instruction; Load and store instructions; Instruction set; Classification of instruction set architectures
Conjunto de instrucciones, Las instrucciones que el procesador central puede ejecutar
jump instruction         
INSTRUCTION IN COMPUTER PROGRAM
Unconditional branching; Jump instruction; Conditional branch; Unconditional branch instruction; Branch instruction; Unconditional branch; Jump (Computer science); Jump (computer science); Branch (instruction); Conditional jump; Branch on condition; Jump target (computing); Branch-free code; Branchless programming; Branchless code; Branchless algorithm
instrucción de salto

Definizione

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decodificador de señales que permite navegar por InternetInternet utilizando como monitormonitor un televisor hogareño.

Wikipedia

Reduced instruction set computer

In computer engineering, a reduced instruction set computer (RISC) is a computer architecture designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a complex instruction set computer (CISC), a RISC computer might require more instructions (more code) in order to accomplish a task because the individual instructions are written in simpler code. The goal is to offset the need to process more instructions by increasing the speed of each instruction, in particular by implementing an instruction pipeline, which may be simpler given simpler instructions.

The key operational concept of the RISC computer is that each instruction performs only one function (e.g. copy a value from memory to a register). The RISC computer usually has many (16 or 32) high-speed, general-purpose registers with a load–store architecture in which the code for the register-register instructions (for performing arithmetic and tests) are separate from the instructions that grant access to the main memory of the computer. The design of the CPU allows RISC computers few simple addressing modes and predictable instruction times that simplify design of the system as a whole.

The conceptual developments of the RISC computer architecture began with the IBM 801 project in the late 1970s, but these were not immediately put into use. Designers in California picked up the 801 concepts in two seminal projects, Stanford MIPS and Berkeley RISC. These were commercialized in the 1980s as the MIPS and SPARC systems. IBM eventually produced RISC designs based on further work on the 801 concept, the IBM POWER architecture, PowerPC, and Power ISA. As the projects matured, many similar designs, produced in the late 1980s and early 1990s, created the central processing units that increased the commercial utility of the Unix workstation and of embedded processors in the laser printer, the router, and similar products.

The varieties of RISC processor design include the ARC processor, the DEC Alpha, the AMD Am29000, the ARM architecture, the Atmel AVR, Blackfin, Intel i860, Intel i960, LoongArch, Motorola 88000, the MIPS architecture, the PA-RISC, the Power ISA, the RISC-V, the SuperH, and the SPARC. RISC processors are used in supercomputers, such as the Fugaku.